Current computer processing systems operate on binary data wherein a logic one is represented by a high voltage level (approximately Vcc, typically 3.3 or 5 Volts) and logic 0 is represented by a low voltage level (approximately Vss, typically 0 volts or ground). Conventional random access memory cells, such as dynamic (DRAM), charge a cell capacitor to the high voltage level to store a logic one and discharge the capacitor to low voltage level to store a logic zero. During a DRAM read, the voltage on a cell capacitor is differentially sensed against a reference voltage set between Vcc and Vss and then, depending on the result, restored by latching the full Vcc or Vss level. Data from the cell is similarly output to the periphery and ultimately outside the DRAM device itself by driving various input/output (I/O) lines to approximately Vcc or Vss.
The ever-increasing memory demands require the storing of more bits per DRAM chip to increase storage capacity. The number of bits per DRAM chip can be increased either by increasing the DRAM cell density (i.e., the number of cells per given chip area), or the DRAM cell capacity (i.e., the number of bits stored in each cell). Increasing the DRAM cell density requires the development of an advanced circuit design and fabrication techniques to pack smaller cells into denser arrays, which is time consuming and requires expensive photolithographic process equipment. Further, as DRAM cells become smaller and the arrays more dense, physical device aspects, such as the charge stored per capacitor, will become limiting factors.
The memory capacity can be increased, for both volatile memory, such as DRAM, and non-volatile memory such as flash memory, by storing multiple bits per cell. In one approach, more than the traditional two voltage levels can be retained in the storage mechanism of a cell with each voltage level representing a different data value. For example, assume that for a given cell, data can be stored as one of four allowed voltage levels. A voltage of 0V can then be used to represent a two-bit logic word “00”, a voltage of approximately 1V to represent a logic “01”, a voltage of approximately 2V to represent a logic “10” and a voltage of approximately 3V to represent a logic “11”. In this fashion, an NSB and a LSB can be stored in a single cell. The exact voltages and the number of voltage levels used depend on the desired design.
The actual implementation of multi-valued memory presents a number of problems. For instance, Murotani et al. (1997 IEEE International Solid State Circuit Conference, Digest of Technical Papers, pp. 74-75, 1997) have proposed a 4-level storage device in which both a most significant bit (MSB) and a least significant bit (LSB) can be stored in a single cell as function of capacitor voltage. The MSB is detected by sensing the stored voltage against a reference voltage that is substantially one-half of Vcc. After sensing the MSB, the LSB is then sensed against one-half of Vcc of offset by approximately one-third Vcc. The sign of the offset (+,−) depends on the MSB (1, 0).
Obtaining an adequate sense signal in such a system disadvantageously requires that the storage capacitor has a large capacitance, which in turn implies a chip area occupied by the storage element or the use of a high dielectric constant material in constructing the capacitor, or possibly a combination of both.
There is a need for providing an elegant circuit for implementing multi-valued storage with efficient use of chip area.